The present invention relates to methods and apparatus for memory access, in particular to memory access in which data is written to and read from memory using a known address incrementing scheme having address jumps.
Random access memory (RAM) may be used in various systems for rearranging data. An interleaver, for example uses a block of memory to write data in one order and then read that data in a different, interleaved, order. An example of such an interleaver is one in which data is written in columns and read in rows, thus rearranging the data in an interleaved fashion. Other examples of such memory arrangements include systems for filtering data or rotating image data. More generally, such systems have an address incrementing scheme in which the read and/or write addressing jumps through data with a defined jump length.
There are two principal types of RAM: Static RAM and Dynamic RAM
In a static RAM, the access time associated with each location is constant and commonly-available parts (such as the 72 Mbit module on the HAPS-51 board) are more than fast enough to operate at the DVB-T2 cell rate (9.14 Mcell/s for 8 MHz system bandwidth). Static RAMs use flip-flops to hold the state of each bit and will maintain their contents as long as they are powered.
Dynamic RAM is based on a different structure. The memory cells are based on capacitive elements that are laid out in a grid of rows and columns and use fewer transistors. In terms of timing, accessing rows is expensive. However once a row is ‘open’ (activated), access to subsequent columns on the same row is considerably faster. Furthermore, Synchronous Dynamic RAMs operate in bursts so that for each requested access to a given column, one or more subsequent columns are also accessed on subsequent clock cycles. Once a row is finished with it must be closed (pre-charged) which acts to re-charge the capacitive cells. There is a maximum time that any given row can be open, i.e. between an activate and a pre-charge, after which too much charge will have leaked from the capacitive cells and the data corrupted. Since the memory cells are based on capacitors, over time the charge in each one leaks away and so the entire chip much be periodically refreshed. This further reduces the effective throughput.
Dual Data Rate (DDR) SDRAM transfers data on both the rising and falling edge of the clock. Thus the maximum transfer rate is twice that of the I/O bus clock speed. DDR2 is a later enhancement that clocks the memory at half the I/O bus clock speed and increases the amount of data that is pre-fetched (locally cached) before it is required on the data bus. As a result, the I/O clock speed of DDR2 can be doubled compared with DDR resulting in transfers at twice the bandwidth.
As previously described, RAM is used in various systems in which there is a need to ‘Jump’ through data. A particular example of use of a memory as described above is in a time interleaver for DVB-T2 TI blocks. The DVB-T2 standards are known to the skilled person, for example in “Digital Video Broadcasting (DVB); Frame structure channel coding and modulation for a second generation digital terrestrial television broadcasting system (DVB-T2) ETSI 302755.”
The DVB-T2 standard supports service-specific robustness through the use of Multiple Physical Layer Pipes (PLPs). Different services carried on different PLPs can be configured with a different code rate and constellation. Furthermore, each PLP can have different time interleaver parameters. Whilst a receiver is only required to be able to receive two PLPs simultaneously, a modulator is required to transmit every PLP and therefore requires a separate time interleaver memory for each PLP.
For Multiple PLP operation, the allocation and scheduling is carried out in a T2-Gateway and carried over the DVB-T2 Modulator Interface (T2-MI) to the modulator for subsequent coding and transmission.
Further storage may also be required in the modulator when In Band Signalling and/or L1-repetition are used. If the T2-Gateway processes incoming TS packets and generates the BB-frames immediately, then the modulator is required to have a further Interleaving Frame's worth of storage per PLP since the In-Band Signalling information for the current Interleaving Frame will only be available at the end of the next Interleaving Frame.
Most modulator implementations are based on Field Programmable Gate Arrays (FPGAs) such as those made by Xilinx and Altera. Whilst these have a reasonable amount of on-board block memory, even a single time interleaver typically requires the use of external RAM. Normally this would be static (SRAM) since it is easy to drive and the time taken to access each location is constant; provided a part of appropriate speed is chosen, the DVB-T2 time interleaver can be mapped directly onto it.
The problem with using an SRAM is that it is very expensive when compared to the large, low cost, Synchronous Dynamic RAM (SDRAM) modules that are prevalent in modern Personal Computers. The downside of SDRAM is the more complicated timing requirements; the time taken to access a given memory location varies enormously and depends on the locations of previous reads and writes.